multiple array matrix high-density eplds fax id: 6100 cy7c340 epld family cypress semiconductor corporation ? 3901 north first street ? san jose ? ca 95134 ? 408-943-2600 december 1988 C revised october 1995 1cy 7 c34 0 e pl d family features ? erasable, user-configurable cmos eplds capable of implementing high-density custom logic functions ? 0.8-micron double-metal cmos eprom technology (cy7c34x) ? advanced 0.65-micron cmos technology to increase performance (cy7c34xb) ? multiple array matrix architecture optimized for speed, density, and straightforward design implementation programmable interconnect array (pia) simplifies routing flexible macrocells increase utilization programmable clock control expander product terms implement complex logic functions ? warp2 ? low-cost vhdl compiler for cplds and plds ieee 1164-compliant vhdl available on pc and sun platforms ? warp3 ? vhdl synthesis viewlogic graphical user interface schematic capture (viewdraw?) vhdl simulation (viewsim?) available on pc and sun platforms general description the cypress mul tiple array matrix (max?) family of eplds provides a user-configurable, high-density solution to gener- al-purpose logic integration requirements. with the combina- tion of innovative architecture and state-of-the- art pro cess, the max eplds offer lsi density without sacrificing speed. the max architecture makes it ideal for replacing large amounts of ttl ssi and msi logic. for example, a 74161 counter util izes only 3% of the 128 macrocells available in the cy7c342b. similarly, a 74151 8-to-1 multiplexer consumes less than 1% of the over 1,000 product terms in the cy7c342b. this allows the designer to replace 50 or more ttl packages with just one max epld. the family comes in a range of densities, shown below. by standardizing on a few max building blocks, the designer can replace hundreds of different 7400 series part numbers currently used in most dig- ital systems. the family is based on an architecture of flexible macrocells grouped together into logic array blo cks (labs). w ithin the lab is a group of additional product terms called e xpander product terms. these expanders are used and shared by the macrocells, allowing complex functions of up to 35 product terms to be easily implemented in a single macrocell. a pro- grammable intercon nect array (pia) globally routes all signals within devices containing more than one lab. this architec- ture is fabricated on the cypress 0.8-micron, double-lay- er-metal cmos eprom process, yielding devices with signif- icantly higher integration, density and system clock speed than the largest of previous gener ation eplds. the cy7c34xb de- vices are 0.65-micron shrinks of the original 0.8-micron family. the cy7c34xbs offer faster speed bins for each device in the cypress max family. the density and performance of the cy7c340 fam ily is ac- cessed using cypresss warp2 and warp3 design software. warp2 provides state-of-the-art vhdl synthesis for max and f lash 370? at a very low cost. warp3 is a sophisticated cae tool that includes schematic capture (viewdraw) and timing simulation (viewsim) in addition to vhdl synthesis. consult the warp2 and warp3 datasheets for more informa- tion about the development tools. max family members feature CY7C344(b) cy7c343(b) cy7c342b cy7c346(b) cy7c341b macrocells 32 64 128 128 192 max flip-flops 32 64 128 128 192 max latches [1] 64 128 256 256 384 max inputs [2] 23 35 59 84 71 max outputs 16 28 52 64 64 packages 28h,j,w,p 44h,j 68h,j,r 84h,j 100r,n 84h,j,r key: pplastic dip; hwindowed ceramic leaded chip carrier; jplastic j-lead chip carrier; rwindowed pin grid array; wwindowed ceramic dip; nplastic quad flat pack notes: 1. when all expander product terms are used to implement latches. 2. with one output. pal is a registered trademark of ad vanced m icro devices. max is a registered trademark of altera corporation. f lash 370 is a trademark of cypress semiconductor corporation. warp2 and warp3 are registered trademarks of cypress semiconductor corporation. viewdraw and viewsim are trademarks of viewlogic corp.
cy7c340 epld family 2 figure 1. key max features dedicated inputs logic block array (lab) expander product terms dual i/o feedback multiple arrays (labs) macrocells programmable interconnect arra y (pia) c340C1
cy7c340 epld family 3 functional description the logic array block the logic array block, shown in figure 2 , is the heart of the max architecture. it consists of a macrocell array, expand- er product term array, and an i/o block. the number of macrocells, expanders, and i/o vary, depending upon the device used. global feedback of all signals is provided within a lab, giving each functional block complete access to the lab resources. the lab itself is fed by the program- mable interconnect array and dedicated input bus. the feedbacks of the macrocells and i/o pins feed the pia, pro- viding access to them through other labs in the device. the members of the cy7c340 family of eplds that have a single lab use a global bus, so a pia is not needed (see figure 3 ). the max macrocell traditionally, plds have been divided into either pla (pro- grammable and, programmable or), or pal? (programma- ble and, fixed or) architectures. plds of the latter type provide faster input-to-output delays, but can be inefficient due to fixed allocation of product terms. statistical analysis of pld logic designs has shown that 70% of all logic func- tions (per macrocell) require three product terms or less. the macrocell structure of max has been optimized to handle variable product term requirements. as shown in figure 4 , each macrocell consists of a product term array and a con- figurable register. in the macrocell, combinatorial logic is implemented with three product terms ored together, which then feeds an xor gate. the second input to the xor gate is also controlled by a product term, providing the ability to control active high or active low logic and to implement t- and jk-type flip-flops. if more product terms are required to implement a given func- tion, they may be added to the macrocell f rom the e xpander product term array. these additional product terms may be added to any macrocell, allowing the designer to build gate-in- tensive logic, such as address decoders, adders, compara- tors, and complex state machines, without using extra macro- cells. the register within the macrocell may be programmed for ei- ther d, t, jk, or rs operation. it may alternately be configured as a flow-through latch for minimum input-to-output delays, or bypassed entirely for purely combinatorial logic. in addition, each register supports both a synchronous preset and clear, allowing asynchronous loading of counters of shift registers, as found in many standard ttl functions. these registers may be clocked with a synchronous system clock, or clocked inde- pendently from the logic array. expander product terms the expa nder product terms, as shown in figure 5 , are fed by the dedicated input bus, the programmable interconnect array, the macrocell feedback, the expanders themselves, and the i/o pin feedbacks. the outputs of the expanders then go to each and every product term in the macrocell array. this allows expanders to be shared by the product terms in the logic array block. one expander may feed all macrocells in the lab, or even multiple product terms in the same macrocell. since these expanders feed the second- ary product terms (preset, clear, clock, and output enable) of each macrocell, complex logic functions may be imple- mented without utilizing another macrocell. likewise, ex- panders may feed and be shared by other expanders, to implement complex multilevel logic and input latches. figure 2. typical lab block diagram figure 3. 7c344 lab block diagram a a a a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a i n p u t s p i a macrocell array expander product term array i/o block i/o pins programmable interconnect array c340C2 a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a i n p u t s macrocell array expander product term array i/o block i/o pins c340?3
cy7c340 epld family 4 figure 4. macrocell block diagram figure 5. expander product terms figure 6. i/o block diagram dedicated inputs programmable interconnect expander product terms 16 macrocell feedbacks i/o output enable array clock clear preset to i/o control note: one system cl ock per lab p q c d programmableflipCflop (d, t,jk,sr) d registeredorflowC throughCla tch operation d programmableclock d asyncclearandpreset macrocell feedback 8 (32 for 7c344) 32 (64 for 7c344) signals to pia c340C4 expander p-terms macrocell p-terms c340C5 to pia (lab for 7c344) i/o output enable from macrocell in lab i/o pad threeCstate buffer c340C6
cy7c340 epld family 5 i/o block separate from the macrocell array is the i/o control block of the lab. figure 6 shows the i/o block diagram. the three-state buffer is controlled by a macrocell product term and the drives the i/o pad. the input of this buffer comes from a macrocell within the asso ciated lab. the fee dback path from the i/o pin may feed other blocks wi thin the lab, as well as the pia. by decoupling the i/o pins from the flip-flops, all the registers in the lab are buried, allowing the i/o pins to be used as dedicated outputs, bidirectional outputs, or as additional dedicated inputs. therefore, applications requiring many buried fli p-flops, such as counters, shift registers, and state machines, no longer consume both the macrocell regis- ter and the associated i/o pin, as in earl ier d evices. the programmable interconnect array pld density and speed has t raditionally been l imited by signal routing; i.e., getting signals from one macrocell to another. for smaller devices, a single array is u sed and all signals are avail- able to all macrocel ls. but as the devices incre ase in density, the number of signals being routed becomes very large, in- creasing the amount of silicon used for interconnections. also, because the signal must be global, the added loading on the internal connection path reduces the overall speed performance of the device. the max archi- tecture solves these problems. it is based on the concept of small, flexible logic array blocks that, in the larger devices, are interc onnected by a pia. the pia solves interconnect limi tations by routing only the sig- nals needed by each lab. the architecture is designed so that every signal on the chip is within the pia. the pia is then programmed to give each lab access to the signals that it requires. consequently, each lab receives only the signals needed. this effectively solves any routing problems that may arise in a design without degrading the performance of the device. unlike masked or programmable gate arrays, which induce variable delays dependent on routing, the pia has a fixed delay from point to point. this eliminates undesired skews among logic signals, which may c ause gl itches in inter- nal or external logic. development software support warp2 warp2 is a state-of-the-art vhdl compiler for designing with cypress plds and cplds. warp2 util izes a proper subset of ieee 1164 vhdl as its hardware description l anguage (hdl) for design entry. vhdl provides a number of significant benefits for the design entry pro cess. warp2 accepts vhdl input, synthesizes and optimizes the entered design, and out- puts a jedec map for the desired device. for functional sim- ulation, warp2/ provides a graphical waveform simulator (nova). vhdl (vhsic hardware description language) is an open, powerful, non-proprietary la nguage that is a standard for be- havioral design entry and simulation. it is already mandated for use by the department of defense, and supported by every major vendor of cae tools. vhdl allows designers to learn a single language that is useful for all facets of the design pro- cess. warp3 warp3 is a sophisticated design tool that is based on the latest version of viewlogics cae design environment. warp3 fea- tures schematic capture (viewdraw), vhdl waveform simula- tion (viewsim), a vhdl debugger, and vhdl synthesis, all integrated in a graphical design environment. warp3 is avail- able on pcs using windows 3.1 or subsequent versions, and on sun and hp workstations. for further information on warp software, see the warp2 and warp3 datasheets contained in this data book. third-party software cypress maintains a very strong commitment to third-party de- sign software vendors. all major third-party software v endors provide support for the max family of devices. to expedite this support, cypress supplies vendors with all per tinent architec- tural information as well as design fitters for our pro ducts. programming the impulse3 ? device programmers from cypress will pro- gram all cypress plds, cplds, fpgas, and proms. the unit is a standalone programmer that connects to any ibm-compatible pc via the printer port. third-party programmers as with development software, cypress strongly supports third-party programmers. all major third-party program mers support the max family. cross reference altera cypress prefix epm prefix: cy prefix: ep prefix: palc 22v10C10c palc22v10dC7c 22v10C10c palc22v10dC10c 22v10C10c pal22v10cC7c+ 22v10C10c pal22v10cC10c+ 22v10C15c palc22v10bC15c 22v10C15c palc22v10dC15c 5032dc 7c344C25wc 5032dcC2 7c344C20wc 5032dcC15 7c344C15wc 5032dcC17 call factory 5032dcC20 7c344C20wc 5032dcC25 7c344C25wc 5032dm 7c344C25wmb 5032dmC25 7c344C25wmb 5032jc 7c344C25hc 5032jcC2 7c344C20hc 5032jcC15 7c344C15hc 5032jcC17 call factory 5032jcC20 7c344C20hc 5032jcC25 7c344C25hc
cy7c340 epld family ? cypress s emiconduc tor corporation, 1995. the information contained herein is s ubject to change without notice. cypress semiconductor corporation assumes no re sponsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it c onvey or imply any license under patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconduc tor products in life-support sy stems application implies that the manufacturer assumes all risk of such use and in doing so indemni fies cypress semiconductor against all charges. document #: 38-00087-d 5032jm 7c344C25hmb 5032jmC25 7c344C25hmb 5032lc 7c344C25jc 5032lcC2 7c344C20jc 5032lcC15 7c344C15jc 5032lcC17 call factory 5032lcC20 7c344C20jc 5032lcC25 7c344C25jc 5032pc 7c344C25pc 5032pcC2 7c344C20pc 5032pcC15 7c344C15pc 5032pcC17 call factory 5032pcC20 7c344C20pc 5032pcC25 7c344C25pc 5064jc 7c343C35hc 5064jcC1 7c343C25hc 5064jcC2 7c343C30hc 5064ji 7c343C35hi 5064jm 7c343C35hmb 5064lc 7c343C35jc 5064lcC1 7c343C25jc 5064lcC2 7c343C30jc 5128agcC12 7c342bC12rc 5128agcC15 7c342bC15rc 5128agcC20 7c342bC20rc 5128ajcC12 7c342bC12hc 5128ajcC15 7c342bC15hc 5128ajcC20 7c342bC20hc 5128alcC12 7c342bC12jc 5128alcC15 7c342bC15jc 5128alcC20 7c342bC20jc 5128gc 7c342C35rc 5128gcC1 7c342C25rc 5128gcC2 7c342C30rc 5128gm 7c342C35rmb 5128jc 7c342C35hc 5128jcC1 7c342C25hc 5128jcC2 7c342C30hc 5128ji 7c342C35hi 5128jiC2 7c342C30hi 5128jm 7c342C35hmb 5128lc 7c342C35jc 5128lcC1 7c342C25jc 5128lcC2 7c342C30jc cross reference (continued) altera cypress 5128li 7c342C35ji 5128liC2 7c342C30hi 5130gc 7c346C35rc 5130gcC1 7c346C25rc 5130gcC2 7c346C30rc 5130gm 7c346C35rm 5130jc 7c346C35hc 5130jcC1 7c346C25hc 5130jcC2 7c346C30hc 5130jm 7c346C35hm 5130lc 7c346C35jc 5130lcC1 7c346C25jc 5130lcC2 7c346C30jc 5130li 7c346C35ji 5130liC2 7c346C30ji 5130qc 7c346C35nc 5130qcC1 7c346C25nc 5130qcC2 7c346C30nc 5130qi 7c346C35ni 5192agcC15 7c341bC15rc 5192agcC20 7c341bC20rc 5192ajcC15 7c341bC15hc 5192ajcC20 7c341bC20hc 5192alcC1 7c341bC15jc 5192alcC2 7c341bC20jc 5192gc 7c341C35rc 5192gcC1 7c341C25rc 5192gcC2 7c341C30rc 5192jm 7c341C35hm 5192jc 7c341C35hc 5192jcC1 7c341C25hc 5192jcC2 7c341C30hc 5192gm 7c341C35rm 5192ji 7c341C35hi 5192lc 7c341C35jc 5192lcC1 7c341C25jc 5192lcC2 7c341C30jc cross reference (continued) altera cypress
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